this book is not suitable for the bookstore catalogue

this book is not suitable for the bookstore catalogue

Oversampling techniques based on sigma-delta modulation are widely used to implement the analog/digital interfaces in CMOS VLSI technologies. This approach is relatively insensitive to imperfections in the manufacturing process and offers numerous advantages for the realization of high-resolution analog-to-digital (A/D) converters in the low-voltage environment that is increasingly demanded by advanced VLSI technologies and by portable electronic systems. In The Design of Low-Voltage, Low-Power Sigma-Delta Modulators, an analysis of power dissipation in sigma-delta modulators is presented, and a low-voltage implementation of a digital-audio performance A/D converter based on the results of this analysis is described. Although significant power savings can typically be achieved in digital circuits by reducing the power supply voltage, the power dissipation in analog circuits actually tends to increase with decreasing supply voltages. Oversampling architectures are a potentially power-efficient means of implementing high-resolution A/D converters because they reduce the number and complexity of the analog circuits in comparison with Nyquist-rate converters. In fact, it is shown that the power dissipation of a sigma-delta modulator can approach that of a single integrator with the resolution and bandwidth required for a given application. In this research the influence of various parameters on the power dissipation of the modulator has been evaluated and strategies for the design of a power-efficient implementation have been identified. The Design of Low-Voltage, Low-Power Sigma-Delta Modulators begins with an overview of A/D conversion, emphasizing sigma-delta modulators. It includes a detailed analysis of noise in sigma-delta modulators, analyzes power dissipation in integrator circuits, and addresses practical issues in the circuit design and testing of a high-resolution modulator. The Design of Low-Voltage, Low-Power Sigma-Delta Modulators will be of interest to practicing engineers and researchers in the areas of mixed-signal and analog integrated circuit design.

"The use of high-speed high-resolution analog-to-digital converters (ADCs) allows part of the signal processing to be done in the digital domain allowing for higher system integration and cheaper fabrication. Becoming more in use, hand-held devices have low-power requirements to allow for longer battery life. Also, designing ADCs in nanometer digital CMOS technologies make them more integrable with digital processing blocks and cheaper. This thesis aims at designing a high-speed (16MS/s conversion rate) high-resolution (12bits) Delta-Sigma modulator with low-power consumption in nanometer CMOS. Delta-Sigma modulators can achieve high resolution in low and medium speed applications. For higher speed applications, the oversampling ratio (OSR) will have to be kept low to avoid inefficient design. However, lowering the OSR requires special care in the design starting from the architecture until the full circuit implementation. In nanometer CMOS technologies, analog properties, such as intrinsic gain, degrade which might result in a higher power consumption. Moreover, the low nominal supply voltages associated with such technologies adds more challenges to the design of a low distortion power-efficient Delta-Sigma modulator. Targeting a specic resolution, lowering the voltage supply usually results in a higher power consumption. This thesis suggests possible solutions to achieve low power consumption while targeting high-speed applications in nanometer low-voltage-supply environment.This thesis presents a low-power Discrete-Time (DT) Delta-Sigma modulator making use of a single-loop multibit DT digital input-feedforward Delta-Sigma architecture. The main feature of this architecture is the reduced signal swings at the output of the integrators which allows the use of a low voltage supply. The low-power Switched-Capacitor (SC) implementation is ensured by using a novel opamp switching technique, optimizing simultaneous opamp's settling in cascaded nondelaying SC integrators, and using non-overlapping clock phases with unequal duty-cycles. The novel opamp switching technique is based on a current-mirror opamp with switchable transconductances. The current-mirror opamp works with full current during the charge-transfer phase while the output current is partially switched off during the sampling phase. Power saving can be achieved while ensuring that the opamp output is available during both phases. The simultaneous settling of series opamps in a two cascaded nondelaying SC integrators scheme is looked at as a two-pole system where power optimization is necessary to ensure minimum power consumption while meeting the settling requirements. The use of clock phases with unequal duty-cycles gives the designer an extra degree of freedom to further power optimize the design. The experimental Delta-Sigma ADC is a 4th-order 5.5bits single-loop Delta-Sigma modulator with an OSR of 8. The design starts with the structural-level aspects in which system-level decisions are made and simulations are carried-out with behavioral models to find the suitable circuit parameters. Circuit-level design in then considered to design each block and simulate the full-system. Fabricated in 1V 65nm CMOS, the Delta-Sigma modulator prototype occupies an active area of 1.2mm2. Although the targeted resolution is about 12bits, the experimental results shows a dynamic range (DR) of 66dB (11bits) over an 8MHz bandwidth while consuming 26mW and a peak SNR/SNDR of 64/58.5dB. The proposed opamp switching technique brings the total power consumption from 29mW to 26mW without affecting the performance (SNDR stays at 58.5dB). The deviation in experimental performance, from simulations, in thought to be due to higher parasitic capacitance requiring higher bias currents which results in drop of opamp dc gain. Compared to state of the art high-speed high-resolution Delta-Sigma modulators operated from 1V supply and fabricated in CMOS, it achieves a reasonable Figure-of-Merit." --

Analog Circuit Design contains the contribution of 18 experts from the 13th International Workshop on Advances in Analog Circuit Design. It is number 13 in the successful series of Analog Circuit Design. It provides 18 excellent overviews of analog circuit design in: Sensor and Actuator Interfaces, Integrated High-Voltage Electronics and Power Management, and Low-Power and High-Resolution ADC’s. Analog Circuit Design is an essential reference source for analog circuits designers and researchers wishing to keep abreast with the latest developments in the field. The tutorial coverage also makes it suitable for use in an advanced design course.

This book presents innovative solutions for the implementation of Sigma-Delta Modulation (SDM) based Analog-to-Digital Conversion (ADC), required for the next generation of wireless hand-held terminals. These devices will be based on the so-called multi-standard transceiver chipsets, integrated in nanometer CMOS technologies. One of the most challenging and critical parts in such transceivers is the analog-digital interface, because of the assorted signal bandwidths and dynamic ranges that can be required to handle the A/D conversion for several operation modes. This book describes new adaptive and reconfigurable SDM ADC topologies, circuit strategies and synthesis methods, specially suited for multi-standard wireless telecom systems and future Software-defined-radios (SDRs) integrated in nanoscale CMOS. It is a practical book, going from basic concepts to the frontiers of SDM architectures and circuit implementations, which are explained in a didactical and systematic way. It gives a comprehensive overview of the state-of-the-art performance, challenges and practical solutions, providing the necessary insight to implement successful design, through an efficient design and synthesis methodology. Readers will learn a number of practical skills – from system-level design to experimental measurements and testing.