Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes. A phase lock loop (PLL) clock multiplier has also been designed using new circuit techniques and successfully tested. 1) A 1.2V, 52mW, 210MS/s 10-bit two-step ADC in 130nm CMOS occupying 0.38mm2. Using offset canceling comparators and capacitor networks implemented with small value interconnect capacitors to replace resistor ladder/multiplexer in conventional sub-ranging ADCs, it achieves 74dB SFDR for 10MHz and 71dB SFDR for 100MHz input. 2) A 32mW, 1.25GS/s 6-bit ADC with 2.5GHz internal clock in 130nm CMOS. A new type of architecture that combines flash and SAR enables the lowest power consumption, 6-bit >1GS/s ADC reported to date. This design can be a drop-in replacement for existing flash ADCs since it does require any post-processing or calibration step and has the same latency as flash. 3) A 0.4ps-rms-jitter (integrated from 3kHz to 300MHz offset for >2.5GHz) 1-3GHz tunable, phase-noise programmable clock-multiplier PLL for generating sampling clock to the SAR ADC. A new loop filter structure enables phase error preamplification to lower PLL in-band noise without increasing loop filter capacitor size.

This book is a step-by-step tutorial on how to design a low-power, high-resolution (not less than 12 bit), and high-speed (not less than 200 MSps) integrated CMOS analog-to-digital (AD) converter, to respond to the challenge from the rapid growth of IoT. The discussion includes design techniques on both the system level and the circuit block level. In the architecture level, the power-efficient pipelined AD converter, the hybrid AD converter and the time-interleaved AD converter are described. In the circuit block level, the reference voltage buffer, the opamp, the comparator, and the calibration are presented. Readers designing low-power and high-performance AD converters won’t want to miss this invaluable reference. Provides an in-depth introduction to the newest design techniques for the power-efficient, high-resolution (not less than 12 bit), and high-speed (not less than 200 MSps) AD converter; Presents three types of power-efficient architectures of the high-resolution and high-speed AD converter; Discusses the relevant circuit blocks (i.e., the reference voltage buffer, the opamp, and the comparator) in two aspects, relaxing the requirements and improving the performance.

Omnidirectional Inductive Powering for Biomedical Implants investigates the feasibility of inductive powering for capsule endoscopy and freely moving systems in general. The main challenge is the random position and orientation of the power receiving system with respect to the emitting magnetic field. Where classic inductive powering assumes a predictable or fixed alignment of the respective coils, the remote system is now free to adopt just any orientation while still maintaining full power capabilities. Before elaborating on different approaches towards omnidirectional powering, the design and optimisation of a general inductive power link is discussed in all its aspects. Special attention is paid to the interaction of the inductive power link with the patient’s body. Putting theory into practice, the implementation of an inductive power link for a capsule endoscope is included in a separate chapter.

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This comprehensive resource provides the latest information on digitization and reconstruction (D&R) of analog signals in digital radios. Readers learn how to conduct comprehensive analysis, concisely describe the major signal processing procedures carried out in the radios, and demonstrate the dependence of these procedures on the quality of D&R. The book presents and analyzes the most promising and theoretically sound ways to improve the characteristics of D&R circuits and illustrate the influence of these improvements on the capabilities of digital radios. The book is intended to bridge the gap that exists between theorists and practical engineers developing D&R techniques by introducing new signal transmission and reception methods that can effectively utilize the unique capabilities offered by novel digitization and reconstruction techniques.

This book describes techniques for realizing wide bandwidth (125MHz) over-sampled analog-to-digital converters (ADCs) in nano meter-CMOS processes. The authors offer a clear and complete picture of system level challenges and practical design solutions in high-speed Delta-Sigma modulators. Readers will be enabled to implement ADCs as continuous-time delta-sigma (CT∆Σ) modulators, offering simple resistive inputs, which do not require the use of power-hungry input buffers, as well as offering inherent anti-aliasing, which simplifies system integration. The authors focus on the design of high speed and wide-bandwidth ΔΣMs that make a step in bandwidth range which was previously only possible with Nyquist converters. More specifically, this book describes the stability, power efficiency and linearity limits of ΔΣMs, aiming at a GHz sampling frequency.

Biopotential Readout Circuits for Portable Acquisition Systems describes one of the main building blocks of such miniaturized biomedical signal acquisition systems. The focus of this book is on the implementation of low-power and high-performance integrated circuit building blocks that can be used to extract biopotential signals from conventional biopotential electrodes. New instrumentation amplifier architectures are introduced and their design is described in detail. These amplifiers are used to implement complete acquisition demonstrator systems that are a stepping stone towards practical miniaturized and low-power systems.