Hardware/software co-verification is how to make sure that embedded system software works correctly with the hardware, and that the hardware has been properly designed to run the software successfully -before large sums are spent on prototypes or manufacturing. This is the first book to apply this verification technique to the rapidly growing field of embedded systems-on-a-chip(SoC). As traditional embedded system design evolves into single-chip design, embedded engineers must be armed with the necessary information to make educated decisions about which tools and methodology to deploy. SoC verification requires a mix of expertise from the disciplines of microprocessor and computer architecture, logic design and simulation, and C and Assembly language embedded software. Until now, the relevant information on how it all fits together has not been available. Andrews, a recognized expert, provides in-depth information about how co-verification really works, how to be successful using it, and pitfalls to avoid. He illustrates these concepts using concrete examples with the ARM core - a technology that has the dominant market share in embedded system product design. The companion CD-ROM contains all source code used in the design examples, a searchable e-book version, and useful design tools. * The only book on verification for systems-on-a-chip (SoC) on the market * Will save engineers and their companies time and money by showing them how to speed up the testing process, while still avoiding costly mistakes * Design examples use the ARM core, the dominant technology in SoC, and all the source code is included on the accompanying CD-Rom, so engineers can easily use it in their own designs

This book originated from a workshop held at the DATE 2005 conference, namely Designing Complex SOCs. State-of-the-art in issues related to System-on-Chip (SoC) design by leading experts in the fields, it covers IP development, verification, integration, chip implementation, testing and software. It contains valuable academic and industrial examples for those involved with the design of complex SOCs.

This book describes a comprehensive combination of methodologies that strongly enhance the modern Virtual Prototype (VP)-based verification flow for heterogeneous systems-on-chip (SOCs). In particular, the book combines verification and analysis aspects across various stages of the VP-based verification flow, providing a new perspective on verification by leveraging advanced techniques, like metamorphic testing, data flow testing, and information flow testing. In addition, the book puts a strong emphasis on advanced coverage-driven methodologies to verify the functional behavior of the SOC as well as ensure its security. Provides an extensive introduction to the modern VP-based verification flow for heterogeneous SOCs; Introduces a novel metamorphic testing technique for heterogeneous SOCs which does not require reference models; Includes automated advanced data flow coverage-driven methodologies tailored for SystemC/AMS-based VPs; Describes enhanced functional coverage-driven methodologies to verify various functional behaviors of RF amplifiers.

Starting with a basic overview of system-on-a-chip (SoC), including definitions of related terms, this new book helps you understand SoC design challenges, and the latest design and test methodologies. You see how ASIC technology evolved to an embedded cores-based concept that includes pre-designed, reusable Intellectual Property (IP) cores that act as microprocessors, data storage devices, DSP, bus control, and interfaces -- all "stitched" together by a User's Defined Logic (UDL).

Given the growing size and heterogeneity of Systems on Chip (SOC), the design process from initial specification to chip fabrication has become increasingly complex. This growing complexity provides incentive for designers to use high-level languages such as C, SystemC, and SystemVerilog for system-level design. While a major goal of these high-level languages is to enable verification at a higher level of abstraction, allowing early exploration of system-level designs, the focus so far for validation purposes has been on traditional testing techniques such as random testing and scenario-based testing. This book focuses on high-level verification, presenting a design methodology that relies upon advances in synthesis techniques as well as on incremental refinement of the design process. These refinements can be done manually or through elaboration tools. This book discusses verification of specific properties in designs written using high-level languages, as well as checking that the refined implementations are equivalent to their high-level specifications. The novelty of each of these techniques is that they use a combination of formal techniques to do scalable verification of system designs completely automatically. The verification techniques presented in this book include methods for verifying properties of high-level designs and methods for verifying that the translation from high-level design to a low-level Register Transfer Language (RTL) design preserves semantics. Used together, these techniques guarantee that properties verified in the high-level design are preserved through the translation to low-level RTL.

This book describes in detail all required technologies and methodologies needed to create a comprehensive, functional design verification strategy and environment to tackle the toughest job of guaranteeing first-pass working silicon. The author first outlines all of the verification sub-fields at a high level, with just enough depth to allow an engineer to grasp the field before delving into its detail. He then describes in detail industry standard technologies such as UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), SFC (SystemVerilog Functional Coverage), CDV (Coverage Driven Verification), Low Power Verification (Unified Power Format UPF), AMS (Analog Mixed Signal) verification, Virtual Platform TLM2.0/ESL (Electronic System Level) methodology, Static Formal Verification, Logic Equivalency Check (LEC), Hardware Acceleration, Hardware Emulation, Hardware/Software Co-verification, Power Performance Area (PPA) analysis on a virtual platform, Reuse Methodology from Algorithm/ESL to RTL, and other overall methodologies.