Reconfigurable computing brings immense flexibility to on-chip processing while network-on-chip has improved flexibility in on-chip communication. Integrating these two areas of research reaps the benefits of both and represents the promising future of multiprocessor systems-on-chip. This book is the one of the first compilations written to demonstrate this future for network-on-chip design. Through dynamic and creative research into questions ranging from integrating reconfigurable computing techniques, to task assigning, scheduling and arrival, to designing an operating system to take advantage of the computing and communication flexibilities brought about by run-time reconfiguration and network-on-chip, it represents a complete source of the techniques and applications for reconfigurable network-on-chip necessary for understanding of future of this field.

Processor designers have been utilizing more processing elements (PEs) on a single chip to make efficient use of technology scaling and also to speed up system performance through increased parallelism. Networks on-chip (NoCs) have been shown to be promising for scalable interconnection of large numbers of PEs in comparison to structures such as point-to-point interconnects or global buses. This dissertation investigates the designs of on-chip interconnection networks for many-core computational platforms in three application domains: high-performance network designs for applications with high communication bandwidths; low-cost networks for application-specific low-bandwidth dynamic traffic; and reconfigurable networks for platforms targeting digital signal processing (DSP) applications which have deterministic inter-task communication characteristics. An on-chip router architecture named RoShaQ is proposed for platforms executing general-purpose applications with dynamic and high communication bandwidths. RoShaQ maximizes buffer utilization by allowing sharing of multiple buffer queues among input ports hence achieves high network performance. Experimental results show that RoShaQ is 17.2% lower latency, 18.2% higher saturation throughput and 8.3% lower energy dissipated per bit than state-of-the-art virtual-channel routers given the same buffer capacity averaged over a broad range of traffic patterns. For mapping applications showing low inter-task communication bandwidths, five low-cost bufferless routers are proposed. All routers guarantee in-order packet delivery so that expensive reordering buffers are not required. The proposed bufferless routers have lower costs and higher performance per unit cost than all buffered wormhole routers -- the smallest proposed bufferless router has 32.4% less area, 24.5% higher throughput, 29.5% lower latency, 10.0% lower power and 26.5% lower energy per bit than the smallest buffered router. A globally asynchronous locally synchronous (GALS)-compatible reconfigurable circuit-switched on-chip network is proposed for use in many-core platforms targeting streaming DSP and embedded applications which show deterministic inter-task communication traffic. Inter-processor communication is achieved through a simple yet effective source-synchronous technique which can sustain the ideal throughput of one word per cycle and the ideal latency approaching the wire delay. This network was utilized in a GALS many-core chip fabricated in 65 nm CMOS. For evaluating the efficiency of this platform, a complete IEEE 802.11a baseband receiver was implemented. The receiver achieves a real-time throughput of 54 Mbps and consumes 174.8 mW with only 12.2 mW (7.0%) dissipated by its interconnects. A highly parameterizable NoC simulator named NoCTweak is also proposed for early exploration of performance and energy efficiency of on-chip networks. The simulator has been developed in SystemC, a C++ plugin, which allows fast modeling of concurrent hardware modules at the cycle-level accuracy. Area, timing and power of router components are post-layout data based on a 65 nm CMOS standard-cell library. NoCTweak was used in many experiments reported in this dissertation.

As modern technologies continue to develop and evolve, the ability of users to adapt with new systems becomes a paramount concern. Research into new ways for humans to make use of advanced computers and other such technologies through artificial intelligence and computer simulation is necessary to fully realize the potential of tools in the 21st century. Advanced Methodologies and Technologies in Artificial Intelligence, Computer Simulation, and Human-Computer Interaction provides emerging research in advanced trends in robotics, AI, simulation, and human-computer interaction. Readers will learn about the positive applications of artificial intelligence and human-computer interaction in various disciples such as business and medicine. This book is a valuable resource for IT professionals, researchers, computer scientists, and researchers invested in assistive technologies, artificial intelligence, robotics, and computer simulation.

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Simulation of brain neurons in real-time using biophysically-meaningful models is a pre-requisite for comprehensive understanding of how neurons process information and communicate with each other, in effect efficiently complementing in-vivo experiments. In spiking neural networks (SNNs), propagated information is not just encoded by the firing rate of each neuron in the network, as in artificial neural networks (ANNs), but, in addition, by amplitude, spike-train patterns, and the transfer rate. The high level of realism of SNNs and more significant computational and analytic capabilities in comparison with ANNs, however, limit the size of the realized networks. Consequently, the main challenge in building complex and biophysically-accurate SNNs is largely posed by the high computational and data transfer demands.Real-Time Multi-Chip Neural Network for Cognitive Systems presents novel real-time, reconfigurable, multi-chip SNN system architecture based on localized communication, which effectively reduces the communication cost to a linear growth. The system use double floating-point arithmetic for the most biologically accurate cell behavior simulation, and is flexible enough to offer an easy implementation of various neuron network topologies, cell communication schemes, as well as models and kinds of cells. The system offers a high run-time configurability, which reduces the need for resynthesizing the system. In addition, the simulator features configurable on- and off-chip communication latencies as well as neuron calculation latencies. All parts of the system are generated automatically based on the neuron interconnection scheme in use. The simulator allows exploration of different system configurations, e.g. the interconnection scheme between the neurons, the intracellular concentration of different chemical compounds (ions), which affect how action potentials are initiated and propagate.

As the complexity of modern embedded systems increases, it becomes less practical to design monolithic processing platforms. As a result, reconfigurable computing is being adopted widely for more flexible design. Reconfigurable Computers offer the spatial parallelism and fine-grained customizability of application-specific circuits with the postfabrication programmability of software. To make the most of this unique combination of performance and flexibility, designers need to be aware of both hardware and software issues. FPGA users must think not only about the gates needed to perform a computation but also about the software flow that supports the design process. The goal of this book is to help designers become comfortable with these issues, and thus be able to exploit the vast opportunities possible with reconfigurable logic.